Device for detecting a key switch operation

ABSTRACT

A device for detecting a key switch operation capable of detecting an operating state of a plurality of key switches which are commonly connected with respect to each row line (block line) at one terminal thereof and commonly connected with respect to each column line at the other terminal thereof, thereby constituting a switch matrix. If a signal is provided on all column lines, the signal is transmitted to a block line through a key switch which is in operation and thereby a block including the key switch in operation is detected. A signal is then supplied from the detected block line to a column line only through the key switch in operation in the detected block. The position of the key switch in operation is known by detecting the columnn line on which the signal arrives. According to an embodiment of the invention, capacitance elements are provided both on the block lines and on the column lines for effecting delivery of the signal by charging and discharging of these capacitance elements. There is also disclosed a construction in which detected blocks are once stored in a memory and positions of key switches in operation in the detected blocks are detected and stored block by block. The stored blocks and key switch positions are codified to produce key codes identifying the key switches in operation.

BACKGROUND OF THE INVENTION

This invention relates to a key switch operation detection devicecapable of efficiently detecting operations of a number of key switches.

Various proposals have been made for detecting an operating state(makingor breaking) of one or more key switches provided in a device such as akeyboard of an electronic musical instrument which has a large number ofkey switches.

There is a conventional device in which conductors are individuallyconnected to respective key switches and outputs delivered on theseconductors are individually detected. This device requires a complicatedwiring and therefore is uneconomical. Besides, this device requires alarge number of connection terminals for connecting such wiring to acircuit utilizing the result of detection of the key switch states sothat it is unsuited for a circuit design employing a semiconductorintegrated circuit in which the number of connection pins available foruse is limited.

There is another proposal according to which key switches are arrangedin a matrix circuit so that each of these key switches will beidentified by a column line (input line) and a row line (output line) onwhich the key switch is disposed and an operating state of each keyswitch is detected by sequentially scanning all of the key switches.Such proposal is disclosed in the issued U.S. Pat. No. 3,882,751. Theproposed device is advantageous in that the number of conductors to beconnected between the outside circuit and the key switches can be saved.This device, however, has a problem that an undesirable time delaysometimes occurs between the actual making or breaking of the keyswitches and detection thereof because all of the key switches must bescanned one by one. Further, time required for detecting the states ofall of the key switches is fixed depending upon the scanning speed sothat if there are only a few key switches in operation among a largenumber of key switches, a substantial waste of time occurs due to thefixed time for detection. To reduce such waste of time, the rate of theclock used in the system must be increased with resulting adverseeffects on the system such as increase in the power consumption.

With a view to improving the disadvantages in the above describedproposal, the applicant has proposed novel key switch detection systemsin its issued U.S. Pat. No. 3,899,951 and copending application Ser. No.602631 now U.S. Pat. No. 4,033,221. These systems basically depend uponscanning of a key switch matrix circuit to detect the operating ornonoperating state of the key switches and the improvement resides inproviding a device for reducing the scanning time by scanning onlynecessary sections from among all the key switches. Such improvement hassucceeded only in reduction of the scanning time, but yet theunavoidable waste of time inherent in the scanning systems has remainedunsettled. Even if the scanning section is limited only to necessarysection(s) in the above scanning systems, the probability that theswitches in a nonoperating state are included in the scanning section(s)is fairly high. Accordingly, such nonoperating key switches must beequally scanned and waste of time still occurs.

Furthermore, if a low rate clock is desirable in a circuit utilizing theresult of detection of the key switches for reasons of simplification ofthe circuit design, reduction of power consumption and reduction ofmanufacturing costs, the above described waste of time accompanying thescanning system must be eliminated. The prior art scanning systemapparently has limitations in eliminating such waste of time.

SUMMARY OF THE INVENTION

It is, therefore, an object of the invention to reduce time required fordetecting the operation of the key switches to a maximum possibleextent.

According to the present invention, each of a number of key switches isconnected at one terminal thereof (e.g. a terminal on a movable contactside) to a first detection circuit and at the other terminal thereof(e.g. a terminal on a stationary contact side) to a second detectioncircuit. In one detection operation mode, signals are applied from thefirst detection circuit to the second detection circuit in parallelthrough the key switches to enable the second detection circuit toperform a necessary detection operation. In another detection operationmode, signals are applied from the second detection circuit to the firstdetection circuit in parallel through the key switches to enable thefirst detection circuit to perform a necessary detection operation. Theoperating or nonoperating state of the key switches is detected inaccordance with results of the detection operation in the first andsecond detection circuits.

The detection operation includes storage of signals and the signals arepassed through key switches in operation and stored in the first or thesecond detection circuit. Checking of the respective key switches ismade simultaneously in parallel and only signals having passed throughthe key switches in operation are stored in the first or the seconddetection circuit. If the object of detection is making of a key switch"the key switch in operation" means a key switch which is ON and if theobject of detection is breaking of a key switch, "the key switch inoperation" means a key switch is OFF.

Describing the basic concept of the present invention more specifically,a number of key switches are divided into blocks and block codes (blockidentifying codes) are assigned to the respective blocks for identifyingeach block, whereas note codes (note identifying codes) are assigned tothe respective key switches in each block for identifying each keyswitch. A common note code is assigned to key switches of the same noteregardless of blocks to which the key switches belong. The key switchescan be individually identified by key codes which are combinations ofthe block codes and the note codes. The key switches of the same noteare commonly connected at one terminal thereof to constitute respectivenote lines which in turn are connected to a note detection circuit (i.e.the first detection circuit) while the key switches of the same blockare commonly connected at the other terminal thereof to constituterespective block lines which are connected to a block detection circuit(i.e. the second detection circuit).

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are block diagrams schematically showing the basicconstruction of the device according to the invention;

FIG. 3 is a block diagram showing an embodiment of the invention inconnection with a key switch circuit and a note detection circuit;

FIGS. 4(a) and 4(b) are block diagrams showing the same embodiment inconnection with a block detection circuit;

FIG. 5 is a diagram showing how each key switch is identified by a blockand a note;

FIG. 6 is a diagram illustrating symbols used for designating logicalcircuits;

FIG. 7 is a block diagram showing an example of a device for generatingmode signals designating various detection operation modes;

FIGS. 8(a) through 8(n) are timing charts for explaining operations ofthe component parts shown in FIGS. 3 and 4;

FIG. 9 is a schematic block diagram showing another embodiment of theinvention in connection with a key switch circuit;

FIG. 10 is a schematic block digram showing still another embodiment ofthe invention in connection with a key switch circuit;

FIG. 11 is a block diagram showing a different example of the notedetection circuit producing a start code;

FIG. 12 is a block diagram showing an operation control circuit relatingto the modified embodiment; and

FIGS. 13(a) through 13(e) are timing charts for explaining production ofcontrol pulses used in the circuit shown in FIG. 12.

DESCRIPTION OF PREFERRED EMBODIMENTS

As shown in FIG. 1, conductors n₁ -n_(n) (note lines) representingrespective notes are connected to terminals 1a (movable contacts)disposed on one side of each key switch in a key switch group 1, whereasconductors b₁ -b_(m) (block lines) representing respective blocks areconnected to terminals 1b (stationary contacts) disposed on the otherside of each key switch in the key switch group 1. The conductors n₁-n_(n) are connected to a note detection circuit 2 and the conductors b₁-b_(m) to a block detection circuit 3. Accordingly, the total number ofthe conductors connected to the key switch group 1 is much less than thetotal number of the key switches. If the total number of the keyswitches in the present embodiment is represented by n×m, the totalnumber of the conductors required is only n+m.

Detection of all of the key switches is completed by implementation ofseveral different detection operation modes (hereinafter briefly to as"operation mode" or "mode").

In the first one of these modes, a signal is supplied from a signalsource 21 of the note detection circuit 2 to all the key switches inparallel via the conductors n₁ -n_(n). The signal is passed only throughthe closed contact of the key switch or key switches in operation to acorresponding one of the conductors b₁ -b_(m). The detected signal (i.e.from which conductor(s) the signal(s) are delivered) is stored in ablock memory 31 of the block detection circuit 3. By this arrangement,the block or blocks in which the key switch or switches in operationexist are detected. The timing of the storing of the detected keyswitches is in synchronization with a first mode signal S₁ designatingthe first mode.

In the second mode, a single block among the block or blocks stored inthe memory 31 is extracted by a single block extraction unit 32 andthereupon a signal is applied through one of the conductors b₁ -b_(m)corresponding to the extracted block to the stationary contacts of therespective key switches of the extracted block. The signal from theblock detection circuit 3 is passed to one or more of the conductors n₁-n_(n) connected to the movable contacts of the respective key switchesfor notes covered by the extracted block and corresponding to the keyswitches in operation. This detected signal (i.e. from whichconductor(s) the signal(s) and delivered) is stored in a note memory 22of the note detection circuit 2. Accordingly, which one or ones of thekey switches in the extracted block are in operation is detected. Theextracting operation in the single block extraction unit 32 and thestoring operation in the note memory 22 are performed in synchronizationwith a second mode signal S₂ designating the second mode.

In the second mode, key switches which are in operation can beindividually identified by combination of a single block name extractedby the single block extraction unit 32 and one or more note names storedin the note memory 22.

It will be understood from the foregoing that one feature of the presentinvention is the construction in which the key switches 1 are connectedbetween the note scanning circuit 2 and the block detection circuit 3and detection of the key switches 1 in operation is made by transmittingsignals in opposite directions through the key switches 1. According tothe invention, the terminals 1a and 1b of the key switches 1 are notfixedly used as either input terminals or output terminals but the inputside and output side of both terminals are reversed depending upon theoperation mode, i.e. whether the operation mode is the first mode or thesecond mode.

If a circuit (not shown) utilizing the result of detection of the keyswitches permits, the output of the single block extraction unit 32 andthe parallel outputs of the respective notes from the note memory 22 maybe directly supplied to the circuit for providing the circuit with theresult of key switch detection. If there are blocks which still remainstored in the block memory 31 without being extracted by the singleblock extraction unit 32, the above described second mode is repeated.More specifically, upon extraction of a certain block stored in theblock memory 31 and completion of the second mode for that block,another block stored in the block memory 31 is extracted in response toa next second mode signal S₂ and the second mode is repeated. In thismanner, the blocks to which the key switches in operation belong andwhich have been detected and stored in the memory 31 in the first modeare extracted one by one in response to the second mode signal S₂. Thus,detection of all the key switches in operation is completed when thesecond mode is completed with respect to all of the Blocks stored in thememory 31.

Assuming, for example, that a pulse width of the mode signals S₁ and S₂respectively is 1 clock time, detection of all of the key switches inoperation is completed in only 2 clock times if the key switches inoperation belong to a single block. Even if the key switches are inoperation in all of the blocks, detection of all of the key switches iscompleted in "m+1" clock times (e.g. 13 clock times if m=12). In theprior key scanning systems, time reqired for detection of all of the keyswitches is 144 clock times in a case where n=12 and n=12.

For convenience in the circuit utilizing the result of detection of thekey switches, the stored notes in the note memory 22 should preferablybe delivered out one by one in series.

According to the invention, for achieving the above objective, a thirdmode is provided for delivering out the note identifying signals of thekey switches in operation from the note memory 22 one by one after thenote identifying signals have been stored in the memory 22.

In the third mode, a single one among the notes (i.e. note identifyingsignals) stored in the note memory 22 is extracted by a stored noteextraction unit 23 as shown in FIG. 2 (in which like component parts aredesignated by the same reference characters) and a signal representingthe extracted note is applied to an encoder 24 to produce a code signal(note code NC) consisting of plural bits and representing the note. Theextracting operation in the extraction unit 23 is performed insynchronization with a third mode signal S₃. This third mode is repeatedin response to the clock of the system unitl the note signals stored inthe note memory 22 have all been extracted by the note extraction unit23 and corresponding note code signals have all be delivered out. Sincethe third mode is implemented only with respect to the notes in the notememory 22, there is no room for occurrence of waste of time. If, forexample, three kinds of notes are stored in the note memory 22, thethird mode concerning a certain block is completed in 3 clock times.Completion of the third mode can be known by exhaustion of the contentsstored in the note memory 22 due to extraction and, upon detection ofthe completion of the third mode, the mode is returned to the secondmode, the single block extraction unit 32 extracting a next stored blockand the note memory 22 memorizing the notes of the key switches inoperation in that block. Then, the third mode is implemented again. Inthe third mode concerning a certain block, the signal representing theblock is stored in a memory-and-encoder circuit 33 of the blockdetection circuit 3 whereby a code signal (block code BC) consisting ofplural bits and representing the block is produced by the circuit 33.Accordingly, the key switches in operation are detected by combinationsof the block codes BC and the note codes NC which are generated insynchronization with each other. The codes of the key switches inoperation are produced one by one in series.

As described above, the operation mode changes from the first mode tothe second mode, third mode (or repetition thereof), second mode, thirdmode . . . When production of the key codes has been completed withrespect to all of the blocks stored first in the block memory 31 (i.e.when the third mode has been completed), the contents of storage in theblock memory 31, have all been extracted and the operation mode nowenters a fourth or stand-by mode. After detection of the stand-by mode,the operation mode returns to the first mode and the above describeddetection operation is repeated. By repetition of the first to thefourth modes, detection of all of the key switches in operation iscarried out from time to time.

According to the invention, not only key switches which are turned ON,but also those which are turned OFF may be detected by a constructionsimilar to the above described one. Such construction may be achieved,for example by inverting polarity of signals which are applied to ordelivered from the detection circuit 2 and 3 through the key switchgroup 1, or by employing break contact type switches as the keyswitches.

One example of the device embodying the invention will now be describedwith reference to FIGS. 3 through 9.

FIG. 3 shows an example of a key switch circuit 10 and a note detectioncircuit 20. FIG. 4 shows an example of a block detection circuit 30connected to the key switch circuit 10 shown in FIG. 3.

A number of key switches KS corresponding to the respective keys on thekeyboard of the electronic musical instrument are provided in the keyswitch circuit 10. These key switches are commonly connected block byblock with respect to the blocks U₁ -U₅, L₁ -L₅ and P₁, P₂ at one inputterminal thereof (stationary contact) and connected to blockinput-output terminals T₁ through T₁₂ vis conductors (block lines) b₁-b₁₂. The key switches are connected at the other terminal thereof(movable contact) to dodes DD and commonly connected by each note of C#,D, . . . A#, B and C. Each of the commonly connected key switch groupsis connected to corresponding one of note input-output terminals H₁ -H₁₂via connectors (note lines)n₁ -n₁₂.

In the present embodiment, the key switches are divided by blocksaccording to octave ranges of the keyboard so that the notes in eachblock literally express the actual note names of the keys. Let us assumethat as shown in FIG. 5, twelve keys of C#˜C are assigned to one octaverange from the lowest note side and that the upper keyboard UK comprises61 keys of a note C of 0th octave through a note C of the fifth octave,the lower keyboard LK comprises 61 keys in the same manner and the pedalkeyboard PK comprises 25 keys of a note C of the 0th octave through anote C of the second octave.

Accordingly, the blocks U₁ -U₅ are assigned to the octave ranges of theupper keyboard UK, the blocks L₁ -L₅ to the octave ranges of the lowerkeyboard LK and the blocks P₁, P₂ to the octave ranges of the pedalkeyboard PK, respectively. Consequently, the notes C#-C in each of theblocks correspond to the note names in the respective octave ranges. InFIG. 3, connections of the key switches are shown in detail with respectonly to the block U₅ (i.e. key switches for the fifth octave of theupper keyboard UK) and the block P₁ (i.e. key switches for the 0th andthe first octave of the pedal keyboard PK). The key switches of theother blocks U₄ -P₂ are likewise connected to the respective conductorsn₁ -n₁₂ for the respective notes C, B, A# . . . , C# and also toconductors b₂ -b₁₁ corresponding to these blocks. As will be apparentfrom FIG. 5, since the 0th octave includes only one note of C, the noteC of the 0th octave (designated here as Co) is incorporated in theblocks U₁, L₁ and P₁ for the first octave. Accordingly, a key switch ofthe note Co is additionally included in each of the blocks U₁, L₁ andP₁. The key switches of the note Co are commonly connected and furtherconnected to a note input-output terminal H₁₃ through a condcutor n₁₃ sothat the note Co can be distinguished from the note C.

Since the keyboard portion (the key switch circuit 10) is spaced awayfrom the electric circuit portion (the detection circuits 20, 30),relatively long wiring is required for the conductors n₁ -n₁₃ and b₁-b₁₂ connecting the key switch circuit 10 to the note detection circuit20 and the block detection circuit 30, and conductor capacitances C_(b),C_(n) are observed. For convenience of explanation, conductorcapacitance on the block side conductors b₁ -b₁₂ is all designated bythe same reference character C_(b) and conductor capacitance on the noteside conductors n₁ -n₁₃ is all designated by reference characters C_(n).It should be noted, however, that conductor capacitance observed on oneof the conductors b₁ -b₁₂ and n₁ -n₁₃ is different from one observed onanother. The present embodiment is so constructed that the conductorcapacitances C_(b) and C_(n) are positively utilized.

The note detection circuit 20 (FIG. 3) is composed of signal deliverycircuits 21-1 through 21-13 corresponding to the signal source 21 (FIGS.1 and 2) and being provided respectively for the note C, B, . . . C# andCo, detected note memory circuits 22-1 through 22-13 corresponding tothe note memory 22 (FIGS. 1 and 2) and a note code production circuit240 corresponding to the encoder 24 (FIG. 2). As to the respectivecircuits 21-1 through 21-13, 22-1 through 22-13 and 23-1 through 23-13,only the circuits 21-1, 22-1, 23-1, 21-13, 22-13 and 23-13 concerningthe notes C and Co are illustrated in detail but the rest of thecircuits are all of the same construction as these circuits concerningthe notes C and Co.

The signal delivery circuits 21-1 through 21-13 are adapted to applyvoltage V_(DD) to the note input-output terminals H₁ -H₁₃ by switchingof transistos TRA provided for each of the notes. The output from thenote input-output terminals H₁ -H₁₃ are applied to the detected notememory circuits 22-1 through 22-13.

The block detection circuit 30 (FIGS. 4(a), (b)) is composed of detectedblock memory circuits 31-1 through 31-12 corresponding to the blockmemory 31(FIGS. 1 and 2) and being provided for the respective blocksU₅, U₄, . . . P₂ and P₁, block priority gate circuits 32-1 through 32-12corresponding to the single block extraction unit 32 (FIGS. 1 and 2), ablock code production circuit 330 corresponding to thememory-and-encoder circuit 33 (FIG. 2), a block code temporary memorycircuit 331(FIG. 4(b)) for temporarily storing output B₁ *-K₂ * of theblock code production circuit 330, a block code output gate circuit 332(FIG. 4(b)) for delivering out the temporarily stored block codes insynchronization with the outputs of the note code production circuit(240(FIG. 3), and signal delivery circuit 34-1 through 24-12(FIG. 4(a))for delivering the block signals extracted in a certain priority orderby the block priority gate circuits 32-1 through 32-12 to the notedetection circuit 20 via the key switch circuit 10.

Only the circuits 31-1, 32-1, 34-1, 31-12, 32-12 and 34-12 concerningthe blocks U₅ and P₁ are illustrated in detail but the circuits 31-2through 31-11, 32-2 through 32-11 and 34-2 through 34-11 concerning theother blocks are of the same construction as the circuits concerning theblocks U₅ and P₁. Although the circuits 21-1 through 21-13, 22-1 through22-13, 23-1 through 23-13, 31-1 through 31-12, 32-1 through 32-12, 34-1through 34-12 are different from each other, circuit elements (i.e. ANDgates, OR gates etc.) of these circuits are designated by the samereference characters irrespective of the kind of block or note so longas such circuit elements perform the same function.

Before describing about operation of the respective circuits, briefexplanation will be made about symbols used in the accompanyingdrawings. Inventers are expressed by the symbol shown in FIG. 6(a), ANDgate by the one shown in FIGS. 6(b) and (c), OR gate by the one shown inFIGS. 6(d) and (e) and delay flip-flops by the one shown in FIGS. (f).An AND gate or OR gate with only a few input lines is represented by thesymbol shown in FIG. 6(b) or FIG. 6(d) and one with a relatively largenumber of input lines is represented by the symbol shown in FIG. 6(c) orFIG. 6(e). In the symbol shown in FIG. 6(c) or FIG. 6(e), one input lineis drawn on the input side of the AND or OR gate and signal transmissionlines are drawn in such a manner that they cross the input line witheach crossing point of the input line and the signal transmission linetransmitting a signal to the input terminal of the AND or OR gate beingmarked by a circle. Accordingly, the logical formula of the AND gateshown in FIG. 6(c) is X=A·B·D, whereas the logical formula of the ORgate shown in FIG. 6(e) is X=A+B+C.

In the embodiment shown in FIGS. 3 and 4, all the key switches inoperation are detected by implementation of the first to the fourthoperation modes described above. The kind of the operation mode to beimplemented is designated by the mode signals S₀ -S₃. The stand-by modesignal S₀ designates the fourth mode (stand-by mode), whereas the firstthrough third mode signals S₁, S₂, and S₃ designate the first, secondand third modes respectively. The minimum width of the signals S₀ -S₃ inequal to the period of generation of the clock pulse φ_(A) so that thewhole instrument operates in synchronism with the clock pulse φ_(A).

The period of the clock pulse φ_(A) can be determined as desired and setat 24 μs in the present embodiment. Besides this clock pulse φ_(A), alow frequency clock LC is used for determining a repetition rate of thekey switch detection operation. The period of this clock LC can bedetermined as desired and should conveniently be 200 μs-1 ms fordetection of the key switches.

FIG. 7 shows one example of a circuit for generating the mode signals S₀-S₃. In a clock edge detection circuit 41, the low frequency clock LC(ofa desired duty factor) is applied to a delay flip-flop DF₃ for delayingit by one clock (φ_(A)) and also to an AND gate A₉ whereby the pulserise of the low frequency clock LC is detected in synchronization withthe clock pulse φ_(A). By this arrangement, a starting pulse(differentiation pulse)TC having a pulse width equivalent to the periodof the clock pulse φ_(A) is produced with a period of the clock LC.Relationship between the clock pulse φ_(A) and the starting pulse TC isas shown in FIGS. 8(a) and 8(b). In a mode control circuit 42 in FIG. 7,the stand-by mode signal S₀ is produced by an AND gate A₁₂ when invertedoutput signals Q₁, QHD 2 of delay flip-flops DF₄, DF₅ are both a signal"1". If the starting pulse TC is generated during presence of thisstand-by mode signal S₀, i.e. during the stand-by mode, the output of anAND gate A₁₄ becomes a signal "1". The signal "1" is applied to thedelay flip-flop DF₄ via an OR gate OR₅ and, consequently, the output Q₁becomes a signal "1" one clock (φ_(A)) later. Since the signal Q₂ isstill signal "1", an AND gate A₁₀ is enabled to produce the first modesignal S₁. Switching from the stand-by mode to the first mode is thuscontrolled by the starting pulse TC.

The operation of the embodiment shown in FIGS. 3 and 4 will now bedescribed with reference also to FIGS. 7 and 8.

In the stand-by mode shown by period t₁ in FIG. 8, the stand-by modesignal S₀ (FIG. 8(c)) is applied to the signal delivery circuits 34-1through 34-12 of the block detection circuit (FIG. 4(a)) and therebybrings the transistors TRB of the circuits 34-1 through 34-12 intoconduction. As a result, wiring capacitance C_(b) of the blockconductors b₁ -b₁₂ is discharged.

As the first mode signal S₁ is produced at the period t₂ (FIG. 8(d)),the signal S₁ is applied to the signal delivery circuits 21-1 through21-13 of the note detection circuit 20(FIG. 3) to bring the transistorsTRA into conduction. This causes voltage V_(DD) to be applied to the keyswitch circuit 10 via the terminals H₁ -H₁₃ to charge the wiringcapacitance C_(n) of the note conductors n₁ -n₁₃. The voltage signal(i.e. the charged voltage of the capacitance C_(n)) is simultaneouslydelivered to the conductors of one or more of the blocks (U₅ -P₁) towhich the key switch or switches KS in operation belong via such keyswitches and fed from the corresponding terminals (T₁ -T₁₂) to the blockdetection circuit 30 (FIG. 4(a)). Accordingly, a signal "1" is producedonly in the terminals among the terminals T₁ -T₁₂ corresponding to theblocks in which the key switches in operation have been detected.

In FIG. 4(a), outputs TU₅ -TP₁ of the terminals T₁ -T₁₂ are respectivelyapplied to the corresponding ones of the detected block memory circuits31-1 through 31-12. More specifically, the signals from the terminals T₁-T₁₂ are applied to AND gates A₁ of the circuits 31-1 through 31-12. Thefirst mode signal S₁ is also applied to the AND gates A₁. Accordingly, asignal "1" is stored in a delay flip-flop DF₁ through the AND gate A₁and an OR gate OR₁ only in the circuits among the circuits 31-1 through31-12 corresponding to the blocks in which the key switches in operationhave been detected. If, for example, the blocks in which the keyswitches in operation have been detected are blocks U₅, U₄, U₃ and P₁, asignal "1" is stored in the flip-flops DF₁ of the circuits 31-1, 31-2,31-3 and 31-12. The above described first mode is implemented during oneclock of the period t.sub. 2.

If a signal "1" is applied in the first mode to any one of the blockmemory circuits 31-1 through 31-12 from the block terminals T₁ -T₂, thissignal is detected by an OR gate OR₇ (FIG. 4(a)) and thereupon anany-block signal AB(FIG. 8(g)) representing existence of a block withrespect to which a key switch in operation has been detected. Thisany-block signal AB is applied to an AND gate A₁₈ of the mode controlcircuit 42 in FIG. 7. Since the first mode signal S₁ is present at thistime, the signals Q₁ and Q₂ are both "1" and, accordingly, the AND gateA₁₈ is enabled and input D₂ of the delay flip-flop DF₅ becomes "1"through an OR gate OR₆. Since input D₁ of the flip-flop DF₄ at this timeis a signal "0 ", the signal Q₁ and Q₂ become both signal "1" at theperiod t₃ (FIG. 8) after lapse of one clock (φ_(A)). Accordingly, an ANDgate A₁₁ is enabled to produce the second mode signal S₂. The delayflip-flops DF₁ of the detected block memory circuits 31-1 through 31-12(FIG. 4(a)) at this time contain the signal "1" and, accordingly, asignal "1" is fed from the delay flip-flops DF₁ storing the signal "1"to OR circuits OR.sub. 2 of the corresponding block priority gatecircuits among the circuits 32-1 through 32-12. The outputs of the ORgate OR₂ of each of the circuits 32-1 through 32-11 is connected to theOR gate OR₂ of the circuit of an immediately subsequent priority orderamong the circuits 32-2 through 32-12. Consequently, if there is any oneblock in which a signal is stored, a signal "1" is delivered out of theOR gate OR₂ of the priority gate circuit 32-12 for the block P₁ which isof the lowest priority order and this signal constitutes a memory blocksignal MB(FIG. 8(h)) representing existence of the block storing thesignal. This signal MB is applied to AND gates A₁₃, A₁₅ and A₁₇ of themode control circuit 42 in FIG. 7. Accordingly, the AND gate A₁₃ isenabled simultaneously with the generation of the second mode signal S₂and thereupon another second mode signal S₂ ' is produced.

In the above described manner, the second mode signals S₂ and S₂ ' aregenerated at the period t₃ and the operation mode enters the secondmode.

In the second mode in which a single block is extracted from among thestored blocks, the extraction is made in a predetermined priority orderin the priority gate circuits 32-1 through 32-12 (FIG. 4(a)). In theembodiment shown in the figure, the priority is given in the order ofthe blocks U₅, U₄ . . . L₅, L₄ . . . P₂, P₁. In the circuit 32-1 for theblock U₅ of the highest priority order, the output of an inverter I₁ isalways a signal "1" so that the AND gate A₃ is enabled upon receipt ofthe signal "1" from the flip-flop DF₁ of the circuit 31-1. The outputsof the flip-flops DF₁ of the memory circuits 31-1 through 31-11 for theblocks U₅ -P₂ of higher priority orders are applied to the inverters I₁and the OR gates OR₂ of the circuits 32-2 through 32-12 for the blocksU₄ -P₁ of the lower priority order. When the signal is stored in thehigher order blocks U₅ -P₂, a signal "O" is applied to the AND gates A₃via the inverters I₁ of the lower order blocks U₄ -P₁ for inhibiting theAND gates A₃. Accordingly, a signal "1" is delivered only from the ANDgate A₃ of a single one of the priority gate circuits 32-1 through32-12.

Assuming that key switches in operation have been detected in the blocksU₅, U₄, U₃ and P₁, a signal "1" is delivered only from the AND gate A₃of the circuit 32-1 for the block U₅ at the period t₃. The outputs ofthe AND gates A₃ of the circuits 32-2 through 32-12 for the other blocksU₄ -P₁ are all signal "0". The outputs of the AND gates A₃ of therespective circuits 32-1 through 32-12 are applied directly to AND gatesA₄ and also applied to AND gates A₅ after being inverted by invertersI₂.

The second mode signal S₂ is applied to the AND gates A₄ and A₅ of thepriority gate circuits 32-1 through 32-12, whereas the other second modesignals S₂ ' is applied to the detected note memory circuits 22-1through 22-13 of the note detection circuit 20 in FIG. 3.

Accordingly, at the period t₃, the output of the AND gate A₄ of thepriority gate circuit 32-1 is a signal "1" and the outputs of the ANDgates A₄ of the other circuits 32-2 through 32-12 are a signal "0".Thus, the storage of the block U₅ only is extracted and the extractedsignal is applied to a block code delivery circuit 330 and thetransistor TRC of the signal delivery circuit 34-1. The output of theAND gate A₄ of the circuit 32-1 is inverted by an inverter I₃ of thecircuit 31-1 of the same block for inhibiting the AND circuit A₂ of thecircuit 31-1. The storage in the flip-flop DF₁ of the circuit 31-1therefore is cleared. However, the outputs of the AND gates A₄ of theother circuits 32-2 through 32-12 are a signal "0", so that a signal "1"from the inverter I₃ is applied to the AND gates A₂ of the circuits 31-2through 31-12 of the same block whereby the output signals of theflip-flops DF₁ of the respective circuit 31-2 through 31-12 areself-held. Accordingly storage in the flip-flops DF₁ of the blocks U₄,U₃ and P₁ is maintained. The outputs of the AND gates A₅ of the othercircuits 32-12 through 32-12 become a signal "1" which is applied totransistors TRD of the corresponding signal delivery circuits 34-2through 34-12.

In the above described manner, the transistor TRC is brought intoconduction and the transistor TRD is brought out of conduction in thesignal delivery circuit 34-1 for the block U₅ while the transistor TRCis brought out of conduction and the transistor TRD is brought intoconduction in the signal delivery circuits 34-2 through 34-12 for theblocks U₄ -P₁.

Accordingly, the voltage V_(DD) is applied to the input-output terminalsT₂ -T₁₂ of the blocks U₄ -P₁ in the key switch circuit 10(FIG. 3),thereby charging the wiring capacitance C_(b) of the conductors b₂ -b₁₂.This causes the diodes DD provided for the key switch groups KS for theblocks U₄ -P₁ to be reversely biased with a result that the key switchesKS of the blocks U₄ -P₁ are electrically disconnected from the noteconductors n₁ -₁₃. On the other hand, since the potential at theinput-output terminal T₁ of the block U₅ drops to the ground potentialthrough the transistor TRC, capacitance C_(b) of the conductor b₁ isdischarged and a signal "0" is applied to the key switch KS of the blockU₅. Thus, the diode DD corresponding to the key switch in operation isbrought into conduction through this diode DD. Since the respective keyswitches of the block U₅ correspond to the notes C, B . . . C·0 and theconductor capacitance C_(n) of the conductors n₁ -n₁₂ for the respectivenotes have been charged during the first mode, the conductor capacitanceC_(n) of the note conductors (n₁ -n₁₂) corresponding to the key switchesin operation is discharged via the diode DD, the key switches, theterminal T₁ and the transistor TRC of the circuit 34-1. If, forinstance, three key switches of the notes C, B and E are ON in the blockU₅, the conductor capacitance C_(n) of the conductors n₁, n₂ and n₉ forthe notes C, B and E is discharged and the capacitance C_(n) of theother conductors n₃ -n₈, n₁₀ -n₁₃ remains in a charged condition.

Consequently, a signal "0" is supplied from terminals H₁, H₂ and H₉ tothe inverters I₄ of the detected note memory circuits 22-1, 22-2 and22-9 whereas a signal "1" is supplied from terminals H₃ -H₈ and H₁₀ -H₁₃to the detected note memories 22-3 through 22-8 and 22-10 through 22-13.Thus, a signal "0" is delivered from the block input-output terminal T₁of the extracted block U₅ to the note input-output terminalscorresponding to the key switches in operation through these keyswitches inoperation, whereby the notes of the key switches in operationare detected.

In the detected note memory circuits 22-1 through 22-13, the signalsfrom the terminals H₁ -H₁₃ are inverted by the inverters I₄ andthereafter applied to AND gates A₆. The AND gates A₆ also receive thesecond mode signal S₂ ' so that a signal "1" is stored in the delayflip-flops DF₂ via the AND gates A₆ and the OR gates OR₃ in the memorycircuits 22-1, 22-2 and 22-9 corresponding respectively to the notes C,B and E of the detected key switches in operation. In the foregoingmanner, the second mode is implemented during the period t₃. For causingthe circuits 22-1 through 22-13 to store the detected notes, the secondmode signal S₂ ' which is different from the second mode signal S₂ isemployed so that the detected note will be stored only when a storedblock exists (MB=1) and no new storage will be made in the third mode aswill be described later.

The second mode finishes in one clock. In the next period t₄ (FIG.8), asignal "1" is produced in parallel from the flip-flops DF₂ of thecircuits 22-1, 22-2 and 22-9 storing the detected notes and supplied tothe note priority gate circuits 23-1, 23-2 and 23-9. The third mode isimplemented during the period t₄.

In the third mode in which a single note among the stored notes isextracted, this extraction is effected in accordance with apredetermined priority order in the note priority gate circuits 23-1through 23-13. In the figure, the priority in extraction is given in theorder of the notes C, B, A#. . . C#, Co. As in the note priority gatecircuits 23-1 through 23-12, the output of an inverter I₅ in the gatecircuit 23-1 for the note C of the first priority order is always signal"1", and an AND gate A₈ is enabled when a signal "1" is applied theretofrom the flip-flop DF₂ of the memory circuit 22-1. The outputs of theflip-flops DF₂ of the higher notes C-C# are applied to the inverters I₅of the lower notes B-Co through OR gates OR₄ and successively inhibitthe AND gates A₈ of the lower order. The outputs of the flip-flops DF₂of the respective memory circuits 22-1 through 22-13 are applied to ANDgates A₇ of the circuits 22-1 through 22-13 while the outputs of theflip-flops DF₂ of the memory circuits 22-1 through 22-12 of the notesc-# which are of higher priority orders are successively applied to ANDgates A₇ of the memory circuits 22-2 through 22-12. The AND gate A₇ ofthe memory circuit 22-1 of the first priority order always receives asignal "O" and, accordingly, the stored contents of the flip-flop DF₂ ofthe circuit 22-1 are not self-held. However, the stored contents of theflip-flops DF₂ of the memory circuits 22-2 through 22-12 of the lowerpriority orders are self-held by the output signal "1" of the flip-flopsDF₂ of the memory circuits 22-1 through 22-12 of the higher priorityorders. -t.sub.

Accordingly, a signal "1" is supplied from the priority gate circuit23-1 of the note C to a note code delivery circuit 240 at the period t₄.At this period, the output s of the other circuits 23-2 through 23-13are a signal "0". Then at a period t₅ (FIG. 8), the stored contents ofthe circuit 22-1 are cleared so that a signal "1" is delivered from thepriority gate circuit 23-2 of the note B. At a next period t₆ (FIG. 8),the stored contents of the memory circuit 22-2 of the note B are clearedand, accordingly the output signal "1" of the memory circuit 22-9 forthe note E storing the signal "1" is applied to the note code deliverycircuit 240 via the priority gate circuit 23-9. In this manner, thethird mode is successively repeated during clock periods (i.e. threeclock periods t₄ -t₆ in the above example) corresponding to the numberof the stored notes in the memory circuits 22-1 through 22-13.

Since the transistor TRA can be driven by any one of the first modesignal S₁ and the third mode signal S₃, the transistor TRA in thepresent embodiment is driven by a first and third mode signal S₁₊₃ whichcan be used both for the first mode and the third mode. Since aprerequisite for entering the third mode is that the operation mode in apreceding one clock is either the second mode or the third mode,arrangements are made so that a signal Q₂ is applied to AND gates A₁₅,A₁₆ and A₁₇ in the mode control circuit 42. The fact that this signal Q₂is "1" signifies that the current mode is either the second mode or thethird mode. When the signal Q₂ and the memory block signal MB from theOR gate OR₂ (FIG. 4(a)) are generated and any note signal AN(FIG. 8(i))is generated upon application to the OR gate OR₈ of a signal "1" whichhas been applied to the flip-flops DF₂ of the detected note memorycircuits 22-1 through 22-13, the AND gate A₁₅ (FIG. 7) is enabled. Theanynote signal AN represents that a signal of the detected note is to bestored in any one of the memory circuits 22-1 through 22-13. Since theAND gate A₁₇ is enabled whenever the AND gate A.sub. 15 is enabled, theinput signals to the flip-flops DF₄ and DF₁₅ are both signal "1" andaccordingly, the signals Q₁ and Q₁ become signal "1" one clock later.When the signals Q₁ and Q₂ are both signal "1", this indicates that thethird mode should be implemented (or being implemented). If the any-notesignal AN is still produced after entering the third mode, the output ofthe AND gate A₁₆ is a signal "1" and this causes the signals D₁, D₂ tobe "1" thereby instructing that the third mode is to be continued. Sincethe operation mode is either the first mode or the third mode when thesignal Q₁ is "1", this signal Q₁ is applied to the transistor TRA (FIG.3) as the first and third mode signal S₁₊₃. If the AND gate A₁₇ (FIG. 7)is enabled and the AND gate A₁₅ is not enabled, the second mode signalsS₂ and S₂ ' are generated again.

When the notes stored in the detected note memory circuits 22-1 through22-12 have all been extracted by repetitive implementation of the thirdmode during the periods t₄, t₅ and t₆, the OR gate OR₈ (FIG. 3) producesa signal "O" and the any-note signal AN becomes "0". This signifies thatthe third mode should be finished with respect to the specific block. Ifthere remain any stored blocks (i.e. the signal MB=1), the second modemust be implemented again. Accordingly, the second mode signals S₂ andS₂ ' are produced again in accordance with the output of the AND gateA₁₇. In the above described example, signals are still stored in thememory circuits 31-2, 31-3 and 31-12 for the blocks U₄, U₃ and P₁ sothat the second mode signals S₂ and S₂ ' are produced at a period t₇(FIG. 8).

In the second mode at the period t₃, the block code delivery circuit 330to which a signal "1" has been applied from the priority gate circuit32-1 (FIG. 4(a)) for the block U₅ produces a block code K₂ *-B₁ *representing the block U₅ and delivers this block code to block codetemporary memory circuit 331 shown in FIG. 4(b). In the block codedelivery circuit 330, the codes for the respective blocks U₅ -P₁ areformed by combining codes K₂, K₁ representing the kind of keyboard andcodes B₃, B₂ and B₁ representing the kind of octave, as shown in thefollowing Table I.

                  TABLE I                                                         ______________________________________                                                    key codes                                                                     Column A    Column B                                                          block codes note codes                                                        K2  K1    B3    B2  B1  N4  N3  N2  N1                            ______________________________________                                                      U       0   1                                                         key-                                                                          board   L       1   0                                                                 P       1   1                                                   block         0               0   0   0                                                     1               0   0   1                                             octave                                                                                2               0   1   0                                                     3               0   1   1                                                     4               1   0   0                                                     5               1   0   1                                                     .sup.-- C#                  0   0   0   0                                     D                           0   0   0   1                                     .sup.-- D#                  0   0   1   0                                     E                           0   1   0   0                                     F                           0   1   0   1                       note          .sup.-- F#                  0   1   1   0                                     G                           1   0   0   0                                     .sup.-- G#                  1   0   0   1                                     A                           1   0   1   0                                     .sup.-- A#                  1   1   0   0                                     B                           1   1   0   1                                     C                           1   1   1   0                       ______________________________________                                    

For example, the code for the block U₅ is composed of a code " O1"representing the upper keyboard U and a code "101" representing thefifth octave. In this code, the bits K₁ (K₁ *) and B₁ (B₁ *) arerespectively signal "1" and the bits K₂ (K₂ *) and B₂ (B₂ *) are signal"0". In the block code delivery circuit 330 an OR gate OR₉ produces asignal of the bit K₂ *, an OR gate OR₁₀ the bit K₁ *, an OR gate OR₁₁the bit B₃ *, an OR gate OR₁₂ the bit B₂ *, an OR gate OR₁₃ the bit B₁ *respectively. Accordingly, the output signal of the priority gatecircuit 32-1 for the block U₅ is applied to the OR gates OR₁₀, OR₁₁ andOR₁₃ and the bits K₁ *, B₃ * and B₁ * become a signal "1". Consequently,a code "01101" is produced as the block code K₂ *, K₁ *, B₃ *, B₂ * andB₁ * representing the block U₅.

In FIG. 4(b), the block code temporary memory circuit 331 has memorycircuits 331a-331e for the respective bits K₂ *-B₁ * of the block code.In the figure, only the memory circuit 331a for the bit K₂ * is shown indetail but the other memory circuits 331-b-331e forthe other bits K₁*-B₁ * are of the same construction as the memory circuit 331a. At theperiod t₃, the block code delivered from the block code delivery circuit330 is applied to the memory circuits 331a-331e, each of the signalsrepresenting the bits K₂ *-K₂ *-B₁ * being applied to its correspondingmemory circuit. In the memory circuits 331a-331e, the block code isstored in delay flip-flops DF₆ via the OR gates OR₁₄. The stored signalin the flip-flops DR₆ if produced one clock later, i.e. at the period t₄and is applied to a block code output gate circuit 332 and alsoself-held at the flip-flop DF₆ via the OR gate OR₁₄. More specifically,since an AND gate A₁₉ receives a stand-by mode and second mode signalS₀₊₂ through the inverter I₆ and this signal S₀₊₂ is a signal "0" in theoperation modes other than the standby or the second mode, i.e. in thefirst or the third mode, an inverted signal is "1" during the periodst₄, t₅ and t₆ and, accordingly, the AND gate A₁₉ is enabled and thecontents of the flip-flops DF₆ are self-held. The signal Q₁ provided bythe mode control circuit 42 (FIG. 7) is utilized as the signal S₀₊₂because the signal Q₁ is "0" in the first or the third mode whereas itis "1" in the second or the stand-by mode.

In the foregoing manner, the block code K₂ *-B₁ * delivered from theblock code delivery circuit 330 in the second mode at the period t₃ asshown in FIG. 8(j) is held in the block code temporary memory circuit331 as shown in FIG. 8(k) in the third mode ranging over the periods t₄-t₆. At the period t₇ at which the operation mode is back in the secondmode, the block code of the block U₅ which has been delayed by one clockby the flip-flops DF₆ of the memory circuit 331 is delivered by thecircuit 331 but this block code is prevented by a block code output gatecircuit 332 (FIG. 4(b)).

The outputs of the temporary memory circuit 331a-331e storing thesignals of the respective bits of the block code are supplied to ANDgates A₂₀ -A₂₄ in the block code output gate circuit 332. The AND gatesA₂₀ -A₂₄ receive also a stored-note signal MN supplied from the notedetection circuit 20(FIG. 3), so that the AND gates are enabled insynchronization with delivery of a note code. The stored-note signal MNis delivered from the OR gate OR₄ of the priority gate circuit 23-13(FIG. 3) for the note Co of the lowest priority order. In the thirdmode, the signal MN (FIG. 8(l), is produced every time the signal "1" issupplied from the flip-flops DF₂ of the detected note memory circuit22-1 through 22-13 to a note code delivery circuit 240 via the prioritygate circuits 23-1 through 23-13.

The note code delivery circuit 240 in FIG. 3 is provided for generatingcodes representing note names each of which consists of a plurality ofbits N₄, N₃, N₂ and N₁. Each note C#, D . . . B, C is codified as shownin the column B of the Table I. In the note code delivery circuit 240,the outputs of OR gates OR₁₅, OR₁₆, OR₁₇ and OR₁₈ constitute the signalsfor the bits N₄, N₃, N₂ and N₁. The outputs of the priority gatecircuits 23-1 through 23-13 corresponding to the respective notes areapplied to the OR gates OR₁₅ -OR₁₈ in accordance with the contents ofthe column B in Table I. Accordingly, contents of the note code N₄, N₃,N₂, N₁ delivered from the circuit 240 in the third mode are "1110"representing the note C at the period t₄, "1110" representing note B atthe period t.sub. 5 and "0100" representing the note E at the period t₆.These note codes are sequentially delivered out as shown in FIG. 8(m).The stored-note signal MN is also produced in synchronization with thenote code as shown in FIG. 8(l).

Accordingly, the AND gates A₂₀ -A₂₄ of the block code output gatecircuit 332 (FIG. 4(b)) are enabled only during the third mode (i.e.periods t₄ -t₆) to continuously produce the block code K₂, K₁, B₃, B₂,B₁ for the block U₅ as shown in FIG. 8(n). Simultaneously, the notecodes N₄, N₃, N₂, N₁ for the notes C, B and E are sequentially produced.The key switches in operation in the key switch circuit 10 can bedetected by key codes which are combinations of the block code K₂ -B₁and the note code N₄ -N₁. Thus, the key codes representing the keyswitches in operation are utilized in a circuit (not shown) requiringsuch key codes.

In the above described manner, detection of the key switches in oneblock is completed by the repetitive implementation of the third modeand only the key codes K₂ -N₁ of the key switches in operation aresuccessively provided in series without wasting time.

The lowest key for the O octave in the column B of Table I is includedin the first octave for convenience of actual wiring arrangements of thekey switches. The block code portion B₃, B₂, B₁ for the lowest key forthe O octave therefore must be provided as "0, 0, 0" a shown in Table I.For this purpose, a signal CoS representing the note C of the Oth octaveis applied through an inverter I₁₇ to the third input terminal of an ANDgate A₂₄ corresponding to the bit B in the block code output gatecircuit 332 (FIG. 4(b)). The signal CoS is the output of the note Cofrom the priority gate circuit 23-13 (FIG. 3) and signifies that thenote code for the note Co has been produced when the output of thecircuit 23-13 is a signal "1". Accordingly, the AND gate A₂₄ of thecircuit 332 is inhibited by application thereto of the signal CoS andthe bit B₁ becomes "0". The code of the O octave is thereby produced.When the note Co is not extracted, the output of the inverter I₇ is asignal "1" and the AND gate A₂₄ is not inhibited.

In case this embodiment is utilized for an electronic musicalinstrument, the AND A₂₅ which receives the outputs of the block codetemporary memory circuits 331a, 331b (FIG. 4(b)), i.e. the keyboardcodes K₂, K₁, is utilized for producing a single pedal keyboard tone.The AND gate A₂₅ detects the code "11" which is the code K₂, K₁ of thepedal keyboard P and supplies a pedal keyboard detection signal PCrepresenting that the detected block belongs to the pedal keyboard tothe detected note memory circuits 22-1 through 22-13 of the detectioncircuit 20(FIG. 3). This signal PC is inverted by an inverter I₈ and theinverted signal "0" is used for inhibiting the AND gate A₇ of the memorycircuits 22-1 through 22-13. Accordingly, the flip-flops DF₂ of thememory circuits 22-1 through 22-13 do not perform self-holding so thatthe notes of the key switches in operation of the pedal keyboard blockdetected in the second mode are stored only for one clock time and onlya single note of the first priority order among the stored notes isextracted. Accordingly, the third mode lasts only during one clock timein the case of the pedal keyboard. If the block is for a keyboard otherthan the pedal keyboard, the signal PC is "0" and the output of theinverter I₈ is a signal "1" so that the AND gate A₇ is not inhibited.The present embodiment in which the pedal keyboard P is divided into thetwo blocks P₁ and P₂ has a function of giving a priority to the block P₂in the production of a single pedal tone. In the block detection circuit30 in FIG. 4(a), a signal TP₂ from the input-output terminal T₁₁ isapplied to the memory circuit 31-11 of the block P₂ and also to an ANDgate A₂₆ through an inverter I₉ for inhibiting the AND gate A₂₆. The ANDgate A₂₆ also receives a signal TP₁ from the input-output terminal T₁₂of the block P₁ and delivers this signal TP₁ to the memory circuit 31-12of the block P₁ only when the AND gate A₂₆ is not inhibited. By virtueof this arrangement a detection signal is stored only in the memorycircuit 31-11 of the block P₂ even in a case wherein a key switch inoperation has been detected in both the block P₁ and the block P₂ in thefirst mode. Consequently, the second mode is not implemented withrespect to the block P₁.

At the period t₇, the second mode signals S₂, S₂ ' are produced again aswas previously described. Since the contents of storage in the memorycircuit 31-1 (FIG. 4(a)) for the block U₅ have already become "0", thestored signal "1" in the memory circuit 31-2 for the block U₄ isextracted by the priority gate circuit 32-2 and a signal "1" is providedby the AND gate A₄ of the circuit 32-2. Thus, the second mode isimplemented with respect to the block U₄ at the period t₇ in the samemanner as at the period t₃. At a next clock period t₈ (FIG. 8), thethird mode is implemented with respect to the detected note of the blockU₄. Assume, for instance, that the key switches for the notes B and A inthe block U₄ the key switch for the note E in the block U₃ and the keyswitch for the note E in the block P₁ are ON, the respective componentparts shown in FIGS. 3 and 7 operate in the same manner as in the abovedescribed case of the block U₅ to produce the signals shown in FIG. 8.Then the second and the third modes are repeated and detection of allthe key switches in operation is completed at a period t₁₃. Morespecifically, the codes N₄ -N₁ l for the notes B and A are produced withthe code K₂ -B₁ for the block U₄ as shown in FIGS. 8(m) and 8(n).Subsequently, the code N₄ -N₁ for the note E is produced with the codeK₂ -B₁ for the block U₃ and the code N₄ -N₁ for the note E with the codeK₂ -B₁ for the block P₁. According to FIG. 8, the starting pulse TC isproduced by the clock edge detection circuit 41 shown in FIG. 7. Since,however, the operation mode at this time is the third mode, the outputsQ₁, Q₂ of the flip-flop DF₄ DF₅ of the mode control circuit 42 are bothsignal "1" and the signal Q₁, Q₂ are both "0" so that the pulse TC isignored. At the period t₁₃, the stored signals in the block memorycircuits 31-1 through 31-12 have all been exhausted and the stored blocksignal MB has therefore become "0". Besides, the stored signals in thenote memory circuits 22-1 through 22-13 have all been extracted and theany-note signal AN has become "0 ". Accordingly, the outputs of the ANDgates A₁₄ -A₁₈ of the mode control circuit 42 become "0" and the inputsD₁, D₂ of the flip-flops DF₄ and DF₅ become "0". Thus, the signals Q₁,Q₂ become "1" at a next clock period t₁₄ causing the AND gate A₁₂ toproduce the stand-by mode signal S₀. The operation mode therefore entersthe stand-by, i.e. the fourth, mode.

If the starting pulse TC is produced in this stand-by mode, the firstmode signal S₁ is produced one clock later in the same manner as hasbeen previously been described (simultaneously with the first and thirdmode signal S₁₊₃). Accordingly, the first mode is implemented again andthen the second and third modes are repeated. In the foregoing manner,the key codes K₂, K₁, B₃, . . . N₄, . . . N₁ are successively deliveredfrom the note code delivery circuit 240 of the note detection circuit 20and the block code output gate circuit 332 of the block detectioncircuit 30. The period of the low frequency clock LC(or pulse TC)determines starting of a series of detection operation. If the detectionoperation prolongs exceeding the period of the clock LC, the repetitiveoperation is conducted by a period which is an integer multiple of theperiod of the clock LC.

In the above described embodiment, the voltage V_(DD) from the circuits21-1 through 21-13 of the note detection circuit 20 and the circuits34-1 through 34-12 of the block detection circuit 30 or ground potentialis applied to the conductor capacitances C_(b), C_(n) of the key switchcircuit 10 only for a short time during which such voltage is requiredto charge or discharge the conductor capacitances C_(b), C_(n).Consequently, in the key switch circuit 10 and other circuits 22-1through 22-13, power is consumed only transiently and not constantly.This reduction in power consumption is very advantageous in the circuitdesign. The invention, however, is not limited to the above embodimentbut may be applied to a case wherein no conductor capacitances C_(b),C_(n) are used. One such example will be described below.

FIG. 9 shows another embodiment of the invention is connection with thekey switch circuit 10. In FIG. 9, illustration of circuits other thansignal delivery circuits 21'-1 through 21'-13 of the note detectioncircuit 20 and circuits 34'-1 through 34'-12 of the block detectioncircuit 30 is omitted because these omitted circuits are of the sameconstruction as those shown in FIGS. 3 and 4. Referring to the signaldelivery circuits 21'-1 through 21'-13 of the note detection circuit 20,the voltage V_(DD) is constantly applied through resistors RR to noteinput-output terminals H₁ -H₁₃ of the key switch circuit 10 and also toinverters I₄ of the detected note memory circuits 22-1 through 22-13.Accordingly, a signal "1" is constantly derived through note terminalsH₁ -H₁₃, note conductors n₁ -n₁₃, diodes DD, key switches in operationblock conductors b₁ -b₁₂ of the blocks to which the key switches inoperation belong and block input-output terminals T₁ -T₁₂, and signalsTU₅ -TP₁ (signal " 1") of the blocks in which the key switches inoperation have been found are supplied to AND gates A₁ of the detectedblock memory switch circuits 31-1 through 31-12 (FIG. 4(a)). As thefirst mode is implemented upon generation of the first mode signal S₁,the detected blocks are stored in the corresponding memory circuits 31-1through 31-12 (FIG. 4()). The the operation mode enters the second modeand signals of the blocks extracted by the block priority gate circuits32-1 through 32-12 (FIG. 4(a)) with a certain order of priority areapplied to transistors TRC of corresponding signal delivery circuits34'-1 through 34'-12 (FIG. 9) thereby enabling these transistors TRC.The circuit between one of the circuits 21'-1 through 21'-13corresponding to the note of the key switch in operation and thegrounded transistor TRC which is now ON conducts through one of theterminals T₁ -T₁₂ for the block in which the transistor TRC is ON, acorresponding one of the block conductors b₁ -b₁₂, the key switch inoperation of the block and diode DD, one of the note conductors n₁ -A₁₃corresponding to the key switch in operation and a corresponding one ofthe note terminals H₁ -H₁₃. As the circuit conducts, a signal "0" isapplied to the inverter I₄ of the note memory circuit corresponding tothe key switch in operation. The note of the key switch in operationthereby is detected and stored in one of the memory circuits 22-1through 22-13, and the second mode is implemented. According to thisembodiment, a constant power is used so that the transistors TRA and TRBfor charging and discharging the conductor capacitances Cb, Cn are notrequired.

The foregoing description has been made with regard to a case where thepresent invention is applied to detection of the depressed key on thekeyboard of an electronic musical instrument. Accordingly, a circuitutilizing the key code K₂ -N₁ composed of the block code and the notecode provided by the note detection circuit 20 and the block detectioncircuit 30 is one which produces a musical tone signal of a pitchdesignated by the detected key code and as well as controls its tonecolor and volume.

It should be noted, however, that the invention can be applied not onlyto an electronic musical instrument but also to an apparatus such as aninput device of a computer in which many switches are employed forefficiently detecting operation of the switches without wasting time.

In the embodiment shown in FIG. 3 and FIG. 4(a), the capacitance C_(n)on the note side is charged in the first mode and the capacitance C_(n)corresponding to the key switch in operation is discharged in the secondmode. The construction may be modified so that the capacitance C_(n) isdischarged in the first mode. In this case, the signal delivery circuits21-1 through 21-13 and 34-1 through 34-12 on the note and block sidesmust be modified to some extent.

FIG. 10 shows an example of such modified signal delivery circuits.Transistors TRA' of signal delivery circuits 21-1 through 1-13 on thenote side are grounded and a first mode signal S₁ (S_(1+s)) is appliedto these transistors TRA', Transistors TRB' of signal delivery circuits34-1 through 34-12 on the block side are connected to a power sourceV_(DD) and a stand-by mode signal So is applied to these transistorsTRB'. Diodes DD are connected in a reverse direction to the embodimentshown in FIG. 3.

When the stand-by mode signal So is generated, voltage V_(DD) is appliedto block terminals T₁ -T₁₂ through the transistors TRB' thereby chargingconductor capacitances C_(b1) -C_(b12) on the block side. Then the firstmode -Cb_(S) ₁ is generated and the transistors TRA' are brought intoconduction thereby discharging conductor capacitance C_(n) on the noteside. In response to this discharging conductor capacitance (Cb₁ -Cb₁₂)corresponding to the block including the key switch in operation isdischarged. The block including the key switch in operation is detectedby this discharging of the conductor capacitance. In the detected block,a signal "0" is produced from a corresponding one of the terminals T₁-T₁₂. This signal is reverted to "1" by an inverter IN and thereafter isapplied to the detected block memory circuits 31-1 through 31-12.

In the second mode, a transistor TRC' of one of the signal deliverycircuit 34-1 through 34-12 corresponding to the single block extractedby the priority gate circuits 32-1 through 34-12 is brought intoconduction and a single conductor capacitance (one of Cb₁ -Cb₁₂)corresponding to the specific block is charged. In the signal deliverycircuits for the rest of the blocks transistors TRD' are brought intoconduction and the rest of the conductor capacitance are all discharged.

Accordingly, a signal is delivered to the note conductors n₁ -n₁₃through the key switch in operation in the single detected block and oneof the conductor capacitances c_(n1) -C_(n13) corresponding to the keyswitch in operation is charged. Thus, the note of the key switch inoperation is detected. Since a signal "1" is produced from one of theterminals H₁ -H₁₃ corresponding to the detected note, the inverter I₄ asshown in FIG. 2 is not required in the detected note memory circuits22 - 1 through 22-13 but the output from the terminals H₁ -H₁₂ isdirectly applied to an AND gate A₆.

Even if there is a leakage resistance in the key switch circuit 10, sucha leakage resistance in no way affects the operation of the circuitaccording to the invention. For example, if the leakage resistance is inthe order of 1 MΩ, and each of capacitance elements C_(n1) -C_(nn) andCb₁ -Cb_(m) is about 1 nF, time constant is 1 nF×1 MΩ=1ms which issufficiently large against the frequency of the clock φ_(A) (about 24 μsin the above example) so that the leakage resistance exercises noadverse effect to the capacitance elements.

The foregoing description has been made with respect to the example inwhich only key codes of keys in operation are generated. A modifiedembodiment of the invention in which a start code is produced in theinterval of generation of the key code will not be described. The startcode is a code which is clearly distinguishable from the key code andused for detecting a key-off state.

The present embodiment is different from the previously described by acircuit shown in FIG. 11 and that the mode signal generation circuitshown in FIG. 11 and that the mode signal generation circuit shown inFIG. 7 is substituted by a mode signal generation circuit shown in FIG.12. The circuit of FIG. 11 is different from the circuit of FIG. 3 inthat a signal SSc is applied to OR gates OR₁₅ -OR₁₈ and is the same asthe circuit of FIG. 3 in other respects. Description will therefore bemade about the different construction particularly about generation ofthe start code. The start code SC is produced upon application of astart code designation signal SSc to a note delivery circuit 240 (FIG.11). The start code designation signal SSc is applied to all of OR gatesOR 15₁₅, OR₁₆, OR₁₇ and OR₁₈ of the note code delivery circuit 240 sothat respective bis N₄, N₃, N₂, N₁, become "1". Contents of therespective bits K₂, K₁, B₃, B₂, B₁, N₄, N₃, N₂, N₁ of the start code SCare "000001111". The contents of the start code SC are clearlydistinguishable from the contents of the key code KC for the detectedkey switch in operation. The start code designation signal SSc isgenerated in the stand-by mode as will be described later and,accordingly, the key code KC is never produced concurrently with thestart code SC and the bits K₂, K₁, B₃, B₂, B₁ at this time are all "0".Accordingly, the start code designation signal SSc need not be appliedto a block code delivery circuit 330 and the contents of the bis K₁ -B₁are "00000" without any particular operation.

The start designation signal SSc is generated under control by a controlcounter 43 of an operation control circuit 40 (FIG. 12) so that thestart code SC is produced substantially regularly. The control counter43 (FIG. 12) is an octanary counter including three delay flip-flopsDF₇, DF₈ and DF₉ corresponding respectively to each digit of a binarynumber of three bits, exclusive OR gates ER₁, ER₂ and ER₃ and AND gatesA₂₇ and A₂₈. Since the conrol counter 43 is an octanary counter, countsused are eight (i.e. 0 through 7 in decimal notation). Whether aspecific count is 7 or not is detected by applying the outputs of theflip-flops DF₇ -DF₉ to the AND gate A₂₉. Number 7 in decimal notation is"111" in binary notation so that the output "1" of the AND gate A₂₉which is produced when all of the three bits are "1" represents thecount 7. When the count is 0 - 6 the output of the AND gate A₂₉ is "0".

As the counting pulse for the counter 43, the starting pulse TC isutilized. If the period of the low fequency clock LC applied fromoutside is approximately 500 μs, the starting pulse TC is also generatedwith an interval of approximately 500 μs. This interval is about 20times as long as that of the clock pulse φ₄. The relation between thelow frequency clock LC and the starting pulse TC is shown in FIS. 13(a)and 13(b). If the perod of the low frequency clock LC is set at about 1ms, the period of the starting pulse TC, i.e. the period of the drivingpulse for the counter 43, is also about 1 ms.

When the count of the counter 43 is other than 7, the output of the ANDgate A₂₉ inverted by the inverter I₁₀ is a signal "1", and the startingpulse TC is applied to the counter 43 via the AND gate A₃₀ and the ORgate OR₁₉. The output GC of the OR gate OR₁₉ is used as the drivingpulse for the counter 43. When the count of the counter 43 is other than7, the driving pulse GC is generated in synchronization with thestarting pulse TC as shown in FIG. 13(d). When the count of the counter43 is 7, the output signal "1" of the AND gate A₂₉ is applied to the ANDgate A₃₁ while the starting pulse TC is also applied to the AND gateA₃₁. The AND gate A₃₁ further receives signals Q₁ and Q₂. When thesignals Q₁ and Q₂ are both "1", the operation mode is in the stand-bymode. The output of the AND gate A₃ 1 is applied not only to the OR gateOR₁₉ to produce the driving pulse GC, but also to the note code deliverycircuit 240 (FIG. 10) as the start code designation signal SSc.Accordingly, conditions under which the start code designation signalSSc, i.e. the start code SC, is generated are (1) that the count of thecounter 43 is 7 and (2) that the starting pulse TC is generated in thestand-by (the fourth) mode.

As was peviously described, one detection operation of all of the keyswitches is started by switching from the stand-by mode to the firstmode upon generation of the starting pulse TC. Detection of all the keyswitches in operation is completed before a next shot of the startingpulse TC is generated and, after the operation mode enters the stand-bymode, detection of key switches in operation is started again upongeneration of the next starting pulse TC. Accordingly, one detectionoperation of all the key switches in operation is implemented in theinterval of generation of the starting pulse TC(i.e. one period of thelow frequency clock LC), and the detection of all the key switches inoperation is repeated in accordance with the pulse TC. However, therecan be a case where one detection operation has not completed within oneperiod of the pulse TC, if many keys are depressed simultaneously. Forexample, if the detection operation has not completed at a time pointtm₁ (FIG. 13) when the pulse TC is generated, the key detection mode isin the second or the third mode. As a result, the AND gate A₃₁ is notgenerated. The driving pulse GC is not produced either so that thecounter 43 maintains the count 7. If the detection operation hascompleted by a time point tm₂ when a next shot of the starting pulse TCis generated, the start code designation signal SSc is generated asshown in FIG. 13(e) and the driving pulse GC is supplied to the counter43.

As will be apparent from the above description, the period of generationof the start code designation signal SSc, i.e. the start code SC, isgenerally determined by the period of the low frequency clock LC and thenumber of stages of the control counter 43 but exceptionally is longerby one period of the clock LC(or two periods in an extremely rear case).In the case of FIG. 13, the period of generation of the start codedesignation signal SSc (start code SC) is about eight times that of theperiod of the clock LC and nine times in an exceptional case. If theperiod of the clock LC is 500 μs the period of generation of the startcode SC is about 4 ms. The employment of the start code is advantageousas the time delay from the start of key operation to the arrival of thestart code prevents the chattering state of the key switch from beingtaken out.

What is claimed is:
 1. A device for detecting a key switch operationcomprising:a key switch matrix circuit including a plurality of keyswitches arranged in rows and columns, said rows representing respectiveblocks of the key switches; first means for detecting simultaneously allblocks in which key switches in operation exist; second means forsimultaneously detecting all columns in a single one of said detectedblocks on which the key switches in operation are disposed, said columndetecting being carried out for one block after another, for each of theseparate blocks detected by said first means; and control means forcausing said second means to implement the column detection for oneblock at a time with respect to each of the blocks detected by saidfirst means; each of said key switches in operation being identified bya combination key code designating the single detected block and thecolumn on which said key switch in operation is disposed.
 2. A devicefor detecting a key switch operation as defined in claim 1 which furthercomprises:third means including block memory means for storing signalsindicative of the block detected by said first means, and blockextraction means for extracting one by one in sequence the detectedblock-indicative signals stored in said block memory means; and fourthmeans including note memory means for temporarily storing signalsindicating the columns which contain key switches in operation in eachblock detected by said second means, and column extraction means forextracting the temporarily stored column indicating signals one by onein sequence; whereby the key switches in operation are detected one byone in sequence.
 3. A device for detecting a key switch operation asdefined in claim 2 which further comprises:means for producing blockcode signals representing the blocks extracted by said block extractionmeans; and means for producing note code signals representing thecolumns of the key switches in operation extracted by said columnextraction means; whereby key codes identifying the key switches inoperation are sequentially produced by said means for producing blockand note codes.
 4. A device for detecting a key switch operation asdefined in claim 3 wherein said first means comprises:as first signaldelivery circuit for supplying signals to said matrix circuit inparallel via conductors corresponding to columns, said supplied signalspassing through the respective key switches in operation and leaving thematrix circuit via conductors corresponding to the blocks; and a blockdetection circuit responsive to the signals supplied by said firstsignal delivery circuit for simultaneously detecting in a certain periodof time all the blocks in which the key switches in operation exist;wherein said second means comprises: a second signal delivery circuitfor supplying signal to said matrix circuit via the conductorcorresponding to a single one of the detected blocks, said signal goingthrough the operated key switches in said single block and leaving thematrix circuit in parallel via the conductors corresponding to rowscontaining operated key switches in that single block; and a columndetection circuit responsive to the signals supplied by said secondsignal delivery circuit for simultaneously detecting all notes of thekey switches in operation in said single block, said fourth means beingconnected to said column detection circuit; wherein said third meanscomprises a circuit for operating said second signal delivery circuitevery time one of the blocks is extracted; and wherein said controlmeans comprises a control circuit which performs the control operationin such a manner that whenever said column extraction means hascompleted extraction of all column indicating signals of one block, saidblock detection circuit extracts a next block.
 5. A device for detectinga key switch operation as defined in claim 1 which further comprisesmeans for producing a finish signal when detection of all of the keyswitches in operation has been finished.
 6. A device for detecting a keyswitch operation in which key switches in a matrix are connected at rowconductor and column conductor terminals thereof to a circuit fordetecting the operation of the key switches, comprising:capacitanceelements provided between each matrix row and column conductor andground; first charging-discharging means for charging or discharging thecapacitance elements provided on the row conductor terminals so that thecharge-discharge condition of each such capacitance element indicateswhether at least one switch in the corresponding matrix row is inoperation; second charging-discharging means for charging or dischargingthe capacitance elements provided on the column conductor terminals onlythrough the key switches in operation in one of the matrix rows in whichthere is at least one switch in operation, as indicated by thecharge-discharge condition of said capacitance element on thecorresponding row conductor terminal; and detection means responsive tothe charge-discharge condition of each capacitance element on the columnconductor terminals, as caused by said second charging-dischargingmeans, for detecting which columns in said one matrix row contain keyswitches in operation.
 7. A device for detecting a key switch operationas defined in claim 6 which further comprises:separate detection meansresponsive to the charge-discharge condition of the capacitance elementsprovided on the row conductor terminals caused by said firstcharging-discharging means; memory means for storing signalsrepresenting the charge-discharge conditions detected by said twodetection means separately on the side of the row conductor terminalsand on the side of the column conductor terminals; and means forsequentially extracting and codifying only the signals stored in saidmemory means.
 8. A system for detecting actuated key switches in amatrix, comprising:source means for providing signals in parallel to allcolumns of said matrix, a block memory having a storage cell associatedwith each row of said matrix, said block memory storing the signalsreceived from said source means via said matrix so as to indicate whichrows contain at least one actuated switch, single block extraction meansfor reading our row-indicating signals stored in said block memory oneat a time, in sequence, and for providing a signal to said matrix alongthe single row corresponding to the currently read-out row-indicatingsignal, a note memory having a storage cell associated with each columnof said matrix, said note memory storing signals received from saidblock extraction means through said matrix so as to indicate whichcolumns in said single row contain actuated switches, note extractionmeans for reading pout column-indicating signals from said note memoryone at a time, in sequence, each such read out column-indicating signaland the concurrently read out row-indicating signal together uniquelyidentifying a corresponding actuated switch in said matrix, and timingcontrol means connected to said block extraction means and to said noteextraction means, for causing said single block extraction means to readout the next sequential row-indicating signal only after all of thecolumn-indicating signals for said single row have been read out by saidnote extraction means.
 9. A system for detecting the operation ofindividual switches in a matrix, comprising:a matrix of row conductorsand column conductors, each switch being connected at an intersection ofsaid matrix, there being a capacitance between each conductor andground, first means for precharging all of the capacitances of eachcolumn conductor, whereby the capacitance of each row conductor which isconnected to any column conductor by at least one closed switch will beinitially charged second means for subsequently charging all of said rowconductor capacitances except one that was previously charged by saidfirst means, said one row capacitances being discharged, whereby all ofsaid column capacitances for column conductors that are connected tosaid one row conductor by a closed switch will be discharged, all othercolumn capacitances remaining charged, and means, responsive to theresultant charge condition of said row and column capacitances, foruniquely indicating the matrix position of closed switches in saidmatrix.
 10. A system according to claim 9 further comprising:encodermeans for producing encoded signals identifying the specific columnconductors having discharged capacitances, and control means, responsiveto completion of read-out by said encoder means, for causing said firstmeans again to precharge all of said column conductor capacitances, andfor causing said second means to charge all of said row conductorcapacitances except another one that was initially charged by said firstmeans, whereby all of said column capacitances for column conductorsthat are connected to said other row conductor by a closed switch willbe discharged, all other column capacitances remaining charged. .Iadd.11. A device for detecting a key switch operation comprising:a keyswitch matrix circuit including a plurality of key switches arrangedelectrically in rows and columns each connected via a unidirectionalelement between row conductors and column conductors, said rowsrepresenting respective blocks of the key switches; first means fordetecting simultaneously all blocks in which key switches in operationexist; second means for simultaneously detecting all columns in a singleone of said detected blocks on which the key switches in operation aredisposed, said column detecting being carried out for one block afteranother, for each of the separate blocks detected by said first means;control means for causing said second means to implement the columndetection for one block at a time with respect to each of the blocksdetected by said first means; first capacitance means provided betweeneach row conductor and ground; first voltage applying means connected tosaid first capacitance means to apply thereto a first level voltagewhich would forward bias said unidirectional elements for a firstpredetermined period as preparation for the block detection; secondcapacitance means provided between each column conductor and ground;second voltage applying means connected to said column conductors toapply thereto a second level voltage which would forward bias saidunidirectional elements for a second predetermined period so that thevoltage of such row conductor that is connected to key switches inoperation is changed from said first level voltage to said second levelvoltage, and this change being detected by said first means; said secondlevel voltage being applied also to said second capacitance means forthis second predetermined period as preparation for the note detection,said first means being arranged to apply said first level voltage to therow conductors of the detected blocks one at a time for a thirdpredetermined period so that the voltage of such column conductor thatis connected to a key switch in operation is changed from said secondlevel voltage to said first level voltage, and this change beingdetected by said seond means; each of said key switches in operationbeing identified by a combination key code designating the singledetected block and the column on which said key switch in operation isdisposed. .Iaddend. .Iadd.
 12. An electronic musical instrumentcomprising a key code generator which is composed of means forsequentially scanning with a first clock a plurality of blocks intowhich a plurality of key switches having contacts to be closed aredivided, a priority selector for selectively outputting with a secondclock closure information of each block sequentially in accordance withpredetermined priority, means for inhibiting the first clock with anoperation signal of the priority selector during its operation totemporarily stop the block scanning and means for converting the outputfrom the priority selector and information of the block scanning to keydata of a binary code and means for detecting completion of one scanningto output a variable frame signal of one frame time determined by thenumber of blocks and the number of closed key switches the convertingmeans operating during each time frame.